Data Communication Schematics

Fig 1: Low Speed Bus - JX200 - 1 of 3

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Fig 2: Low Speed Bus - JX200 - 2 of 3

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Fig 3: Low Speed Bus - JX200 - 3 of 3 and JX300

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Fig 4: High Speed Bus - 1 of 2

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Fig 5: High Speed Bus - 2 of 2

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Fig 6: LIN Bus

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Fig 7: Serial Data Communication Enable and Wake-up Circuits

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Fig 8: High Speed Bus (HP2)

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Fig 9: Powertrain Expansion Bus (HP2)

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Fig 10: Serial Data Gateway (SDG) Module (HP2)

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