DTC 33, Data Clock CKT Shorted To Battery Or CCM Internal Open: Notes

Data clock circuit provides timing signal which causes the 160-bit data stream signal to be clocked into LCD buffer. Data clock circuit is brought low by CCM for about 80 milliseconds during CCM power-up. CCM takes samples of data clock circuit during the last 40 milliseconds to ensure circuit is responding to CCM command.

DTC 33 will set when CCM senses high samples on data clock circuit when samples should be low during CCM power-up.

When DTC 33 is set, SYS will flash. DTC 33 will clear when CCM does not sense high samples on data clock circuit during CCM power-up.