DTC 34, Data Clock Circuit Open Or Shorted To Ground: Notes

Data clock circuit provides timing signal which causes the 160-bit data stream signal to be clocked into LCD buffer. Data clock circuit is brought low by CCM for about 80 milliseconds during CCM power-up. CCM takes samples of data clock circuit during the last 40 milliseconds to ensure circuit is responding to CCM command.

DTC 34 will set when CCM senses low samples on data clock circuit when samples should be high during CCM power-up.

When DTC 34 is set, SYS will flash. DTC 34 will clear when CCM does not sense low samples on data clock circuit during CCM power-up.