Bus +/- Signals Open From Driver's Door Module (DDM)
NOTE:
Ensure PCI bus communication between other modules exists before proceeding. If PCI bus module communication does not exist between other modules, go to appropriate system test.
- Turn ignition off. Disconnect DDM connector C1. DDM is part of master switch panel on driver's door panel. Using DVOM, measure voltage between DDM connector C1 terminal No. 1 (Tan/Light Blue wire) and ground. See Fig 1. If voltage is greater than 10 volts, go to next step. If voltage is less than 10 volts, repair open or short to ground in Tan/Light Blue wire between DDM and junction block. Perform BODY VERIFICATION TEST under VERIFICATION TESTS.
- Using DVOM, measure resistance between DDM connector C1 terminal No. 4 (Black wire) and ground. If resistance is less than 10 ohms, go to next step. If resistance is greater than 10 ohms, repair open in Black wire between DDM and ground. Perform BODY VERIFICATION TEST under VERIFICATION TESTS.
- Use Scope Input Cable (CH7058), Cable-To-Probe Adapter (CH7062) and Red and Black test probes. Connect scope input cable to channel one connector on scan tool. Attach Red and Black test probes and cable-to-probe adapter to scope input cable. Select scan tool STANDALONE function. Select LAB SCOPE. Select LIVE. Select 12 VOLT SQUARE WAVE. Press F2 for scope display. Press F2 and use down arrow to select voltage range to 20 volts. Press F2 after selecting 20 volts. Connect Black test probe lead to ground and Red test probe lead to DDM connector C1 terminal No. 9 (Yellow/Violet wire). Turn ignition on. Observe voltage readings on scan tool. If reading pulses from zero to approximately 7.5 volts, go to next step. If reading is steady at zero volts, repair PCI bus circuit (Yellow/Violet wire) between DDM and diagnostic junction port. See appropriate wiring diagram in DATA LINK CONNECTORS article in WIRING DIAGRAMS. Perform BODY VERIFICATION TEST under VERIFICATION TESTS.
- Replace DDM. See appropriate POWER WINDOWS article. Perform BODY VERIFICATION TEST under VERIFICATION TESTS.